The present invention generally relates to voltage source inverters. More particularly, the present invention relates to control techniques for pulse width modulation (PWM) voltage source inverters.
Multilevel pulse width modulation (PWM) voltage source inverters are useful in a variety of applications, and function generally to provide a specific voltage output on a multilevel DC bus. A typical voltage source inverter includes a number of semiconductor switches connected between the positive DC bus and the negative DC bus, and a controller is operatively coupled to control the semiconductor switches to achieve a desired output voltage on the multilevel DC bus.
Numerous techniques to control the semiconductor switches are known. For example, U.S. Pat. No. 5,790,396 discloses a neutral point clamped (NPC) inverter control system which includes a DC power source to output DC voltage having a neutral point, an NPC inverter to convert the DC voltage into AC voltage in three phases through PWM control, a mode selecting unit to decide a first and a second PWM modes by comparing amplitude of voltage reference with a prescribed value that is defined by a minimum pulse width, a first voltage reference conversion means to add a prescribed bias value at which a polarity changes to positive/negative within a fixed period to secure the minimum pulse width to voltage references in respective phases in a first PWM mode, a second voltage reference conversion means to fix the voltage reference in one phase by a value that secures the minimum pulse width when voltage reference in one phase is smaller than a prescribed value that is defined by the minimum pulse width in a second PWM mode and correct voltage references of other two phases so as to make line voltage to a value corresponding to the voltage reference, and a modulation frequency change-over means to lower PWM control modulation frequency in the first PWM mode and to suppress power loss caused by switching in the first PWM mode. In this control system, the PWM frequency is lowered to suppress power loss.
Another control technique is disclosed in U.S. Pat. No. 5,684,688. This patent discloses a three-level NPC inverter topology including two auxiliary resonant commutation circuits which are controlled to clamp the voltage across each main inverter switch to zero voltage prior to altering the state of the switch in order to achieve soft switching of all main inverter switches while reducing output voltage harmonics and gradients. In this technique, a soft switching control scheme is provided by added control circuitry to reduce power losses in the switches.
Other control schemes are believed to include de-rating the inverter at a low frequency by lowering the maximum current output of the inverter, and using a stall protection based on an inverter thermal model to predict device temperatures, which will generate a fault shutdown of the inverter if device temperature limits are exceeded.
Control schemes such as those described above do not address the problem of switch control at lower VSI frequencies. At high frequencies, switches change state frequently. At lower frequencies, the switches change state less frequently; thus, certain switches may be held in an active state for a increased period of time. This results in increased thermal losses for certain switches, and limits the inverter current capability at these lower frequencies.
It would be desirable for a voltage source inverter to be controlled in such a manner that the inverter current capability can be maximized at lower VSI frequencies. It would also be desirable to avoid an uneven distribution of thermal losses for the VSI switches. It would further be desirable to provide improved switch control without adding additional control circuitry.
The present inventions overcomes the disadvantages noted above, and achieves additional advantages, by providing for a voltage source inverter which includes a DC link, a plurality of switches connected in series between the positive and negative dc buses for each phase, and a controller operatively connected to a gate on each of the switches; in the embodiments described below, the controller operates to gate the switches in a substantially uniform manner such that each switch in the plurality of switches has a substantially uniform duty cycle at frequencies below a threshold frequency. The controller makes use of multiple switching states which achieve the same output voltage. The controller minimizes the dwell time of at least one (e.g., zero vector) switching state by maintaining the dwell time below a dwell time threshold. At higher frequencies, the VSI controller can operate according to a standard control technique.
The present invention thus provides a relatively uniform duty cycle for each switch at lower frequencies, thereby avoiding uneven thermal distribution and maximizing the inverter current capability at lower frequencies. The present invention also avoids the use of additional circuitry.